1. Field of the Invention
The present invention relates to a buffer circuit and a potential detecting circuit using the buffer circuit, and in particular relates to a buffer circuit for transmitting an input signal to a circuit in a subsequent stage as well as a potential detecting circuit for detecting whether an input potential reaches a target potential or not, and transmitting a signal depending on the result of detection to a circuit in a subsequent stage.
2. Description of the Background Art
Conventional semiconductor memory devices are provided with high-potential generating circuits for generating high potentials VPP higher than a power supply potential VCC.
FIG. 6 is a block diagram showing a structure of such a high-potential generating circuit. In FIG. 6, the high-potential generating circuit is provided with a charge pumping circuit 71 and a potential detecting circuit 72.
Charge pumping circuit 71 is controlled by a control signal VO', and supplies a predetermined amount of positive charges onto a line carrying high potential VPP in synchronization with clock signal CLK. Potential detecting circuit 72 detects whether the potential on the line of high potential VPP is higher than a target potential VPPR or not, and thereby applies a signal VO' at the level corresponding to the result of detection to charge pumping circuit 71.
When the potential on the line of high potential VPP is lower than target potential VPPR, control signal VO' attains the "L" and thus active level so that charge pumping circuit 71 is activated to supply positive charges onto the line of high potential VPP. When the potential on the line of high potential VPP is higher than target potential VPPR, control signal VO' attains the "H" and thus inactive level so that charge pumping circuit 71 is deactivated to stop supply of the positive charges onto the line of high potential VPP. Accordingly, target potential VPPR is kept on the line of high potential VPP.
FIG. 7 is a circuit diagram showing a structure of potential detecting circuit 72 shown in FIG. 6. Referring to FIG. 7, potential detecting circuit 72 includes a voltage dividing circuit 75, a differential amplifier 76 and a buffer circuit 77. Voltage dividing circuit 75 includes resistance elements 78 and 79 which are connected in series between the line of high potential VPP and the line of ground potential GND. Resistance elements 78 and 79 have predetermined resistance values R2 and R1, respectively. Voltage dividing circuit 75 issues an output potential VI equal to (VPP.times.R1/(R1+R2)) to differential amplifier 76.
Differential amplifier 76 includes P-channel MOS transistors 81 and 82 as well as N-channel MOS transistors 83-85, and determines whether output potential VI of voltage dividing circuit 75 is higher than a reference potential VR or not. Thereby, differential amplifier 76 issues signal VO at the level corresponding to the result of this determination. Signal VO is at "L" and therefore active level when output potential VI of voltage dividing circuit 75 is lower than reference potential VR, and is at "H" and therefore inactive level when output potential VI of voltage dividing circuit 75 is higher than reference potential VR.
In other words, when potential VPP is lower than target potential VPPR=VR.times.(R1+R2)/R1, signal VO is at "L" and therefore active level. When potential VPP is higher than target potential VPPR, signal VO is at "H" and therefore inactive level. Signal VO is applied to buffer circuit 77 formed of inverters 86 and 87 which are connected in series and are arranged in even stages (two stages in the figure). Output signal VO' of buffer circuit 77 is applied to charge pumping circuit 71 in FIG. 6. Therefore, the line of high potential VPP is kept at the level of target potential VPPR=VR.times.(R1+R2)/R1.
In potential detecting circuit 72, however, high potential VPP may stay near target potential VPPR. In this case, output potential VI of voltage dividing circuit 75 stays near reference potential VR so that differential amplifier 76 carries substantially equal potentials on its two inputs, and output signal VO stays near an intermediate level VCC/2. Thereby, a through current flows in inverters 86 and 87, resulting in increase in current consumption.
Accordingly, a buffer circuit which can suppress increase in current consumption due to the through current has been proposed (see Japanese Patent Laying-Open No. 5-335898). FIG. 8 is a circuit diagram showing a structure of such a buffer circuit.
In FIG. 8, the buffer circuit includes inverters 91-93 and 95, and a latch circuit 94. Inverter 93 includes a P-channel MOS transistor 96 and an N-channel MOS transistor 97 which are connected in series between a line carrying power supply potential VCC and a line carrying ground potential GND. Input signal VO is supplied to a gate of P-channel MOS transistor 96 via an inverter 91, and is also supplied to a gate of N-channel MOS transistor 97 via an inverter 92. Inverter 92 has a threshold potential VT2 lower than a threshold potential VT1 of inverter 91.
Latch circuit 94 includes inverters 98 and 99 which are connected in an inverse-parallel manner, and latches the output signal of inverter 93. The output signal of latch circuit 94 is inverted to form signal VO' by inverter 95.
In the buffer circuit, threshold potential VT2 of inverter 92 is lower than threshold potential VT1 of inverter 91 so that MOS transistors 96 and 97 of inverter 93 are not turned on simultaneously. Accordingly, a through current does not flow in inverter 93 even when input signal VO stays near the intermediate level VCC/2.
Even in such a case that input signal V4 is at a level between VT2 and VT1, and both MOS transistors 96 and 97 of inverter 93 are turned off, latch circuit 94 holds the output node of inverter 93 and the input node of inverter 95 at "H" or "L" level. Therefore, a through current does not flow in inverters 95, 98 and 99.
In the above buffer circuit, however, a through current flows in inverters 91 and 92 in the initial stage, and therefore the current consumption increases when input signal VO stays near intermediate level VCC/2.
A buffer circuit in FIG. 9 is a modification of the buffer circuit in FIG. 8, and employs NAND gates 101 and 102 in place of inverters 91 and 92. Input signal VO is applied to one of input nodes of each of NAND gates 101 and 102. A chip enable signal CE is applied to the other input node of each of NAND gates 101 and 102.
When signal CE is at "L" level and the chip is inactive, the outputs of NAND gates 101 and 102 are fixed to "H" level, and a through current does not flow in the buffer circuit. When signal CE is at "H" level and the chip is active, NAND gates 101 and 102 operate as inverters with respect to input signal VO. In this case, the buffer circuit in FIG. 9 performs the same operation as the buffer circuit in FIG. 8.
In this buffer circuit, therefore, the through current does not flow when the chip is inactive, but the through current flows in NAND gates 101 and 102 when input signal VO stays near the intermediate level VCC/2 during the active state of chip.